A FIR filter may be included in the general class of devices referred to as digital signal processors (DSP). This does not mean that the FIR can operate only on digital signals, however. A "digital signal" is a signal that conveys a discrete number of values. Contrast the "analog signal," i.e., a signal that conveys an infinite number of values. A signal having a digital form may be generated from an analog signal through sampling and quantizing the analog signal. Sampling an analog signal refers to "chopping" the signal into discrete time periods and capturing an amplitude value from the signal in selected ones of those periods. The captured value becomes the value of the digital signal during that sample period. Such a captured value is typically referred to as a sample. Quantizing refers to approximating a sample with a value that may be represented on a like digital signal. For example, a sample may lie between two values characterized upon the digital signal. The value nearest (in absolute value) to the sample may be used to represent the sample. Alternatively, the sample may be represented by the lower of the two values between which the sample lies. After quantization, a sample from an analog signal may be conveyed as a digital signal. This is the resultant signal upon which the FIR filter may operate.
Generally speaking, a DSP transforms an input digital signal to an output digital signal. For the FIR filter, the transformation involves filtering out undesired portions of the received digital signal. An original analog signal may be represented as a sum of a plurality of sinusoidal signals. Each sinusoidal signal oscillates at a particular and unique frequency. Filtering is used to remove certain frequencies from an input signal while leaving other frequencies intact.
A FIR filter is a device in which an input sample produces a finite number of output samples. After the finite number of samples expires, the FIR filter output is no longer affected by that particular input sample. Transversal filters, of which FIR filters may be a class, are filters in which a certain number of past samples are used along with the current sample to create each output sample.
FIR filters typically employ an instruction set and hardware design for programming of desired signal filtering. A program is a list of instructions which, when executed, performs a particular operation (i. e., a signal transformation). Programs executing on FIR filters often do so in "real-time". Real-time programs are programs that must execute within a certain time interval. Regardless of whether a program executes in a large period of time or a small period of time, the result of executing the program is the same. However, if real-time programs attempt to execute in an amount of time longer than the required time interval, then they no longer will compute the same result. Programs executing on a FIR filter are real-time programs in that the instructions are manipulating a sample of a digital signal during the interval preceding the receipt of the next sample. If the program cannot complete manipulating a sample before the next sample is provided, then the program will eventually begin to "lose" samples. A lost sample does not get processed, and therefore the output signal of the FIR filter no longer contains all of the information from the input signal provided to the FIR filter.
A FIR filter may be programmed to modify signals. The number of instructions required to do this is relatively fixed. A FIR filter must be capable of executing this relatively fixed number of instructions on any given sample before the next sample of the series is provided.
Besides considering a FIR filter's throughput, all design parameters are associated with a cost. One important cost factor is the silicon area needed to manufacture the FIR filter. Those which are manufactured on a relatively small silicon die are typically less expensive than those requiring a large silicon die. Therefore, an easily manufacturable, low cost FIR filter is desirable.
FIR filters often include memory devices, such as registers, ROM or RAM, to store instructions and samples. It is typical that more transistors are used to form the memory devices than those used to form other FIR filter circuitry. Sometimes the memory-to-other transistor ratio can exceed 2:1. Therefore, it is also important to minimize the size of the included memory devices. However, the size and location of the memory device directly affects throughput. Memory devices configured on the same silicon substrate as the FIR filter may be accessed significantly faster than memories configured on separate substrates. Therefore, large memory devices configured on the same silicon substrate as the FIR filter are desired.
Die area may be maintained while increasing the effective size of the instruction memory by decreasing the size of individual instructions. One method of decreasing the size of an instruction is to encode the information in as few bits as possible. Unfortunately, these instructions require complicated decoding circuitry to determine which of the instructions is currently being executed. Such decoding circuitry also may require a large silicon area or a large amount of time to execute, or both. A cost-effective, high performance instruction set solution is therefore needed to enhance existing FIR filters.
Some features of FIR filters that are important to the design engineer include phase characteristics, stability (although FIR filters are inherently stable), and coefficient quantization effects. To be addressed by the designer are concerns dealing with finite word length and filter performance. When compared with other filter options such as infinite impulse response (IIR) filters, only FIR filters have the capability of providing a linear phase response and are inherently stable, i.e., the output of a FIR filter is a weighted finite sum of previous inputs. Additionally, the FIR filter uses a much lower order than a generic Nyquist filter to implement the required shape factor. This carries a penalty of non-zero inter-symbol interference (ISI), however.
Coefficient quantization error occurs as a result of the need to approximate the ideal coefficient for the "finite precision" processors used in real systems. The net result due to approximated coefficients is a deviation from ideal in the frequency response.
Quantization error sources due to finite word length include:
a) input/output (I/O) quantization, PA1 b) filter coefficient quantization, PA1 c) uncorrelated roundoff (truncation) noise, PA1 d) correlated roundoff (truncation) noise, and PA1 e) dynamic range constraints. PA1 s=scaling factor PA1 x(n)=input PA1 y(n)=output PA1 reduces the throughput time. PA1 reduce the throughput "noise" by eliminating multiplication steps. PA1 improves the choice of available multiplier circuitry. PA1 reduces the number of operations for pre-multiplication to four. PA1 avoids re-calculation at high speeds because coefficients do not change value at high data rates. PA1 allows the use of a low-propagation-delay passgate multiplexer since data are further encoded in "hot one" mode.
Input noise associated with the analog-to-digital (A/D) conversion of continuous time input signals to discrete digital form and output noise associated with digital-to-analog conversion are inevitable in digital filters. Propagation of this noise is not inevitable, however.
Uncorrelated roundoff errors most often occur as a result of multiplication errors. For example, in attempting to maintain accuracy for signals that are multiplied, only a finite length can be stored and the remainder is truncated, resulting in "multiplication" noise being propagated. Obviously, any method that minimizes the number of multiplication steps will also reduce noise and increase inherent accuracy.
Correlated roundoff noise occurs when the products formed within a digital filter are truncated. These include the class of "overflow oscillations". Overflows are caused by additions resulting in large amplitude oscillations. Correlated roundoff also causes "limit-cycle effect" or small-amplitude oscillations. For systems with adequate coefficient word length and dynamic range, this latter problem is negligible. However, both overflow and limit-cycle effects force the digital filter into non-linear operation.
Constraints to dynamic range, such as scaling parameters, are used to prevent overflows and underflows of finite word length registers. For a FIR filter, an overflow of the output produces an error. If the input has a maximum amplitude of unity, then worst case output is: ##EQU1##
Where:
Guaranteeing y(n) is a fraction means that either the filter's gain or the input has to be scaled down by "s". Reducing gain implies scaling the filter coefficients to the point where a 16-bit coefficient, for example, would no longer be used efficiently. Another result of this scaling is to degrade frequency response due to high quantization errors. A better alternative is to scale the input signal. Although this results in a reduction in signal-to-noise ratio (SNR), the scaling factor used is normally &lt;2, which does not change the SNR drastically.
A typical example of a high-speed FIR with five or more coefficients is a Type II FIR. A Type II FIR is based on an array of costly Multiply and Add (MAC) accumulation stages. A conventional system using MAC is constrained to a minimum number of gates to achieve a given partial product accuracy. Digital implementation of an FIR filter is also limited by the maximum number of logic gates that can be inserted between reclocking stages established by the filter's clock cycle. Thus, for a given digital process, a minimum time to process is established by the propagation time through the critical path. To achieve very high speeds of processing, the critical path is filtered and broken into a number of shorter paths that can be addressed at higher clock speeds, i.e., processed within a short clock cycle.
Some conventional high-speed systems employing FIR filters use an analog FIR filter placed before an analog-to-digital (A/D) converter. This prevents the FIR filter's latency from accumulating in the sampled timing recovery loop. This method is inherently not well suited to digitally intensive designs.
Some existing designs always include the FIR filter in the timing recovery loop, increasing latency ab initio, and decreasing stability of the embedded loops, both the timing recovery and gain loops, for example.
Other designs bypass the FIR filter during acquisition but require the coefficients of the FIR filter to be symmetric in order to avoid a phase hit when switching back the FIR filter at the end of the acquisition period.
In magneto-resistive (MR) heads using FIR filters, with their inherent response nonlinearities, this constraint is becoming even more unacceptable. There are more modern methods that achieve a fully digital solution, such as Cirrus Logic's proprietary Interpolated Timing Recovery, but these are extremely complex while covering a disproportionately large area on a silicon chip, for example. In one design, discrete time analog values are entered in memory as are weights, some of which are set to zero to improve throughput, and do not pass through delay lines.
There have been several novel approaches to achieving performance improvement of FIR filters. One involves converting a digital signal to log values, thus avoiding the use of multipliers.
A second more traditional technique uses oversampling.
Yet another approach uses variations of multiplexing, i.e., a multiplexed data stream is input to a tapped delay line and the filter provides a multiplexed output of alternated samples.
For those data streams that have a high dynamic range, a method involving splitting the sampled input signal into two portions and addressing each separately in separate filters has been proposed. Of course, this doubles the number of operations and the hardware required.
To reduce hardware complexity and computational intensity for relatively low-speed applications, such as modems, cascaded arrangements of data registers receive digitally encoded data and sequentially clock the samples. Each data register has a data capacity &gt;2 the code width of a digitized sample, permitting each channel to store both I and Q data. Because the data capacity need be &gt;2 the input, the data rate of devices with which this can be used is relatively low.
Some of the above introduce additional complexity not required in the preferred embodiments of the present invention while others may not be suitable for high-speed applications.
The most straightforward digital FIR filters use the "signed 2's complement" numbering system. This numbering system is noted for its simplicity, and is more than adequate for low-speed FIR filters such as might be used for modems and the like. Other digital FIR filters use a Radix-4 numbering system, which, although offering some improvement, does not fully exploit a 6-bit binary data format. Finally, some architectures have used Radix-8 numbering for the sole purpose of encoding coefficients.